Chip scale package with flip chip interconnect

ABSTRACT

A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as  70  micrometers pitch. Also, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern relation to the positions of the second level interconnections between the package and the printed circuit board. According to this aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority from Provisional Application No.60/272,237, filed Feb. 27, 2001.

BACKGROUND

[0002] This invention relates to high performance semiconductor devicepackaging and, particularly, to chip scale packages having flip chipinterconnection.

[0003] So-called chip scale packages have come into increasing useparticularly, by virtue of their very small size, for packagingintegrated circuit chips in handheld or portable electronicapplications. Wire bonding has been the most widely used technique forinterconnecting the input/output pads of the integrated circuit chipwith the package.

[0004] Flip chip interconnection is considered a promising alternativeto wire bonding, in view of the potential of flip chip interconnectionto provide further decrease in the package size, and in view of thehigher electronic performance that flip chip interconnection canprovide.

[0005] Various techniques of flip chip interconnection have beenproposed for use in chip scale packages. These include interconnectionby solder reflow, and “particulate” interconnection easing anisotropicconductive adhesives “ACAs” or isotropic conductive adhesives “ICAs”.Each of these techniques presents challenges.

[0006] The technique of solder reflow interconnection inherently employsa melting and flow of the interconnect material, and this presentsdifficulties in forming interconnects at very fine geometries. Inparticular, as a practical matter currently the smallest interconnectionpitch for solder reflow interconnection is of the order of 160micrometers. It is desirable for very small size packaging to reliablyform interconnects at finer geometries than this pitch permits.

[0007] In particulate interconnect techniques, whether ACAs or ICAs,conductive particles, such as particles of nickel, of a gold-coatedpolymer, or of silver, are held by mechanical pressure to form theinterconnect. Generally, particulate interconnect structures areincapable of carrying high electrical currents, and they lack long-termreliability because of the particulate nature of the interconnection.

[0008] Chip scale packages employing flip chip interconnection generallyare plagued by poor long-term reliability of the connections between thechip scale package and the printed circuit board to which they areattached to form the electronic subassembly, the so-called second levelinterconnections. This problem arises from the fact that the secondlevel interconnections typically are located in the shadow of theintegrated circuit chip, in order to achieve miniaturization. As aresult of this configuration, there is a large mismatch in the effectivecoefficient of thermal expansion of the chip scale package and theprinted circuit board, and this causes excessive stress in theinterconnections and may eventually lead to failure of theinterconnections by mechanical fatigue over time.

[0009] A chip scale package is desired that provides the advantages offlip chip interconnection while avoiding the disadvantages presented byconventional package configurations.

SUMMARY

[0010] According to the invention, a flip chip package features asolid-state bond technique for connecting the input/output pads on theintegrated circuit chip and the package substrate. The solid-state bondtechnique involves a direct mating of metal surfaces, and does notemploy any particulate conductive material. Accordingly the connectionsare capable of carrying very high current, and display good long-termreliability as compared to ACA or ICA particulate interconnects.Moreover the solid-state bond technique does not entail a melting orflow of any interconnecting material. Accordingly the connections can beformed at very fine geometries, typically as low as 70 micrometerspitch.

[0011] Also according to the invention, the space between the surface ofthe integrated circuit chip and the subjacent surface of the packagesubstrate is filled with a patterned adhesive structure, which consistsof one or more adhesive materials that are deployed in a specifiedpattern in relation to the positions of the second levelinterconnections between the package and the printed circuit board.According to this aspect of the invention, the coefficient of thermalexpansion and the compliancy of the package structure in the regionsoverlying the second level connections can be tailored to reducepotentially damaging propagation of stress generated in the second levelconnections on the package to features on the integrated circuit chip,and thereby extending the long-term reliability of the package and ofthe interconnects.

[0012] In one general aspect, therefore, the invention features a flipchip package including an integrated circuit chip having interconnectbumps formed on input/output pads in a specified arrangement, and apackage substrate having a plurality of bond pads in a complementaryarrangement. The interconnect between the bumps on the integratedcircuit chip and the respective bond pads on the package substrate isestablished by direct mating of the bump surfaces with the respectivebond pads and thermo-mechanical deformation of the bumps. Thethermo-mechanical process entails heating while forcing the bump againstthe pad.

[0013] In some embodiments the bump is constructed of a material orcombination of materials selected to provide low yield strength, highductility, and an oxidation- and corrosion-resistant surface. In someembodiments the bumps are formed of gold or a gold alloy. In someembodiments the bumps are formed on the input/output pads of theintegrated circuit chip by a “stud bumping” or a “solder bumping” or anelectroplating process.

[0014] In another general aspect, the invention features a method forforming a flip chip package, by: providing an integrated circuit chiphaving interconnect bumps formed on input/output pads in a specifiedarrangement, each interconnect bump having low yield strength, highductility, and an oxidation- and corrosion-resistant surface; providinga package substrate having a plurality of bond pads in an arrangementcomplementary to the specified arrangement of input/output pads on theintegrated circuit chip; contacting the bumps with the respective bondpads on the package substrate; and thermo-mechanically treating thebumps to form solid-state connections of the bumps with their respectivebond pads.

[0015] In some embodiments, the thermo-mechanically treating stepincludes concurrently heating and applying a force between the bumps andthe pads. Usually the bump and pad are heated to a temperature in therange about 150° C. to about 300° C., typically about 240° C. for a goldbump; and the force is provided by weighting with a mass in the rangeabout 25 grams to about 150 grams per bump, typically about 50 grams perbump for gold bumps.

[0016] In another general aspect, the invention features a flip chippackage configured for second level interconnection to a printed circuitboard by way of interconnect structures formed in the shadow of thechip. According to this aspect of the invention, a flip chip packageincludes an integrated circuit chip having interconnect bumps formed oninput/output pads in a specified arrangement in a surface of the chip,and a package substrate having a plurality of bond pads in acomplementary arrangement in a subjacent surface of the packagesubstrate. In preferred embodiments the chip-to-package interconnectbumps are bonded to the respective bonding pads in a solid-state manner.Second level interconnect sites are arranged in a second surface of thepackage substrate, and second level interconnect structures areconnected to the respective second level interconnect sites. Between theintegrated circuit chip and the package substrate is a fill volume,which is at least partly filled with one or more fill materials eachhaving a selected specific elastic modulus, including a lower elasticmodulus material in regions of the fill volume that overlie the secondlevel interconnect sites.

[0017] In some embodiments, the fill volume includes a first fill zonemade up of a plurality of generally columnar volumes, generallyoverlying the plurality of second level interconnect sites, and thesecond fill zone constituting the remainder of the fill volume. In someembodiments, at least a part of the first fill zone contains a firstmaterial having a lower specific elastic modulus, and at least a part ofthe second fill zone contains a second material having a comparativelyhigh specific elastic modulus. In some such embodiments the first fillmaterial has a specific elastic modulus less than about 0.5 GPa; and thesecond fill material has a specific elastic modulus greater than about 5GPa, usually in the range about 5 GPa to about 15 GPa. In someembodiments the second fill material includes an epoxy, such as ananhydride curable epoxy. In some embodiments the second material isdeployed in a patterned filling substantially only the second fill zone,so that in the assembled package the generally columnar volumes of thefirst fill zone constitute voids in the fill material within the fillvolume. In other embodiments the first fill material includes anadhesive, such as a silicon adhesive.

[0018] In another general aspect, the invention features a method formaking a flip chip package configured for interconnection to a printedcircuit board, by: providing an integrated circuit chip having asurface; providing a package substrate having a first surface and asecond surface, the second surface being provided with a plurality ofsecond level interconnect sites, the locations of the second levelinterconnect sites defining a plurality of first fill zone areas overthe first surface of the package substrate, the remainder of the firstsurface of the package substrate constituting a second fill zone area;dispensing at least a second fill material, having a specific elasticmodulus greater than about 5 GPa, and usually in the range about 5 GPato about 15 GPa, within the second fill zone area on the first surfaceof the package substrate; and assembling the integrated circuit chip andthe package substrate so that the second fill material is confined in asecond fill zone within a volume defined between the integrated circuitchip surface and the first surface of the package substrate. In someembodiments the method for includes, prior to assembling the package,dispensing a first fill material, having a specific elastic modulus lessthan about 0.5 GPa within the first fill zone area on the first surfaceof the package substrate. In some embodiments, the fill materialdispensing includes deposition, for example by syringe; sheetlamination; and printing, including screen printing.

BRIEF DESCRIPTION OF THE DRAWING

[0019] The FIGURE is a diagrammatic sketch in a sectional view showingan embodiment of a chip package according to the invention.

DETAILED DESCRIPTION

[0020] The invention will now be described in further detail byreference to the drawing, which illustrates an embodiment of theinvention. The drawing is diagrammatic, showing features of theinvention and their relation to other features and structures, and isnot made to scale. For improved clarity of presentation, certain detailsof conventional aspects of the structure of the device illustrated, notnecessary to an understanding of the invention, are omitted from thedrawing.

[0021] Turning now to the FIGURE, there is shown in a diagrammaticsectional view a flip chip package according to the invention generallyat 10 positioned over a conventional printed circuit board generally at40 to which the flip chip package is to be attached by way of secondlevel connections. Printed circuit board 40 includes, among otherstructures not shown in the FIGURE, a substrate 42 and a plurality ofsecond level interconnect pads, for example 44.

[0022] Flip chip package 10 includes integrated circuit chip 12interconnected with package substrate 14. The chip-to-package substrateinterconnection is made by way of interconnect bumps 20 formed on aspecified arrangement of input/output pads (not shown in the FIGURE) ina surface 13 of the integrated circuit chip 12, and correspondingbonding pads 22 in a specified complementary arrangement in a subjacentsurface 15 of the package substrate 14. The interconnect bumps 20 areformed on the input/output pads by a conventional technique, such as bystud bumping or solder bumping or electroplating.

[0023] According to the invention, the interconnect bumps 20 are bondedto the respective bonding pads 22 in a solid-state manner. That is tosay, the interconnect bumps 20 are formed of a non particulateconductive material having low yield strength and high ductility andproviding an oxidation- and corrosion-resistant surface; and the bond isformed by mating the bumps 20 with the respective bonding pads 22 andthermo-mechanically deforming the bumps on the pads. Thethermo-mechanical deformation is carried out by concurrently heating andapplying a force between the bumps and the pads. Usually the bump andpad are heated to a temperature in the range about 150° C. to about 300°C., and the force is provided by weighting with a mass in the rangeabout 25 grams to about 150 grams per bump. Where the bumps are of gold,for example, a satisfactory solid state connection of the bump and padcan be achieved by heating to a temperature about 240° C. and weightingwith a mass about 50 grams per bump. Preferably the bumps are formed ofgold or a gold alloy, but other materials may be used, provided they arenon particulate and conductive, and have sufficient characteristics ofyield strength and ductility to form an adequate bond with the bondingpads by the thermo-mechanical process.

[0024] Connection of the flip chip package 10 to the printed circuitboard 40 is made by way of bumps or balls, for example 38, which areattached to second level interconnect sites, for example 36, in a secondsurface 37 of the flip chip package substrate 14. As the flip chippackage 10 is moved toward the printed circuit board 40 (as illustratedby arrows 39) and the second level interconnect balls 38 are pressedagainst the respective second level interconnect pads 44 and processedto complete the connection, forces generated in the second levelinterconnect are propagated upward into the package substrate, localizedparticularly near the interconnect sites 36. Moreover, in the completeddevice, differences between the thermal expansion coefficients ofelements of the secondary interconnection and of elements of the packagecan result in stresses caused by differential expansion of the variouspart during thermal cycles of the device while in use. These forces andstresses can cause failures, particularly in interconnect structures.These deleterious effects of these are mitigated according to theinvention by providing for dispersion of the forces and stresses in thefill volume between the chip and the package substrate.

[0025] Between the integrated circuit chip 12 and the package substrate14 is a fill volume 30, generally defined as the volume between thesurface 13 of the integrated circuit chip 12 and the subjacent surface15 of the package substrate 14.

[0026] According to the invention, a material deployed within the fillvolume 30 has a selected specific elastic modulus and, particularlyaccording to the invention, the fill volume is filled with one or morematerials including a lower elastic modulus material in regions of thefill volume that overlie the second level interconnect sites. As aresult the package has greater compliance, at least in the regions overthe second level interconnect sites, so that forces resulting frommovement of or differential thermal expansion or contraction near thesecond level interconnect sites are not directly translated upward orlaterally through the fill volume. Stated another way, the lower modulusmaterial provides for distribution over a wider and less focused area ofstresses directed upward through the printed circuit board from theunderlying second level interconnect sites. This reduces localizedstresses on the various parts of the package during manufacture and heatcycling, and improves manufacturing yield and reliability.

[0027] Accordingly, the fill volume 30 includes a first fill zone madeup of a plurality of generally columnar volumes, for example 32,generally overlying the plurality of second level interconnect sites,for example 36, and a second fill zone constituting the remainder of thefill volume 30, for example 34, and including the regions of the bumpsand pads 20, 22.

[0028] In some embodiments of the invention at least a part of the firstfill zone (that is, at least a portion of the columnar volumes 32)contains a first material having a comparatively low specific elasticmodulus, typically less than about 0.5 GPa; and at least a part of thesecond fill zone contains a second material having a comparatively highspecific elastic modulus, typically greater than about 5 GPa, andusually in the range about 5 GPa to about 15 GPa. In some embodiments,no material is deployed within the first fill zone; that is, the secondmaterial is deployed in a pattern filling substantially only the secondfill zone 34, so that when the package is assembled the columnar volumes32 constitute voids in the second fill material within the fill volume30. Stated another way, in such embodiments the first fill materialconstitutes whatever mixture of gases (which may be air) is present inthe voids in the patterned second material at the time of assembly ofthe chip onto the substrate. More usually, according to this aspect ofthe invention, at least a part of the first fill zone (that is, at leasta portion of the columnar volumes 32) contains an adhesive having a lowspecific elastic modulus, such as a silicone adhesive. Adhesivessuitable for use as a first material may have a specific elastic modulusabout 0.4 GP for example. In such embodiments the second fill materialmay be an epoxy, such as for example an anhydride curing epoxy.

[0029] Usually, the fill material or fill materials are applied onto thefirst surface of the substrate prior to assembly of the integratedcircuit chip onto the substrate. This may be particularly advantageouswhere the fill materials include a heat-curable fill material. That is,the non cured fill material is applied onto the substrate, andthereafter the interconnect bumps on the integrated circuit chip aremated to their corresponding pads on the substrate, displacing any fillmaterial between the bumps and the pads. Then the curing of the adhesiveoccurs concurrently with the formation of the interconnect bonds.

[0030] The patterned deployment of the fill material or fill materialsaccording to the invention can be carried out using any of a variety ofmethods, including screen printing, and dispensing by syringe, sheetlamination, or other methods, or combinations of these. Particularly,for example, where only a second fill material is deployed (and thefirst fill zone constitute voids), the second fill material may bescreen printed in the desired pattern on the first surface of thesubstrate prior to assembly of the integrated circuit chip onto thepackage substrate. And, where a low specific elastic modulus adhesivesuch as a silicone adhesive is used as a first fill material, thesilicone adhesive can be spot deposited onto the first surface of thesubstrate, for example by syringe, and then second fill material can beapplied by screen printing to fill the second fill zone around the firstfill material.

[0031] In other embodiments of the invention at least a part of thesecond fill zone and of the first fill zone contain a fill materialhaving an intermediate specific elastic modulus, typically in the rangeabout 1 GPa to about 5 GPa or, in some embodiments, as high as about 10GPa.

EXAMPLE 1

[0032] Dimensions of the columnar volumes constituting the first fillzone.

[0033] As described generally above, the first fill zone is generallydefined as being made up of regions of the fill volume that overly thesecond level interconnect sites. The second level interconnect sitesare, typically, roughly circular pads on the second surface of thesubstrate. A projection of the circular outline of such a second levelinterconnect pad is toward the integrated circuit chip in a directionroughly normal to the substrate surface defines a roughly cylindricalboundary within the fill volume overlying the second level interconnectpad. A “region of the fill volume that overlies a second levelinterconnect site”, as that expression is used herein, is a portion ofthe fill volume that contains at least 90 percent of, and more usually100 percent of, the volume contained within this cylindrical boundary;and usually a “region of the fill volume that overlies a second levelinterconnect site” has itself a generally cylindrical shape whosecross-section at any point within the region contains at least 90percent of, and more usually 100 percent of, the area of a cross-sectionof this cylindrical boundary; and usually the circumference of such across-section of a “region of the fill volume that overlies a secondlevel interconnect site” is roughly a circle that does not extendsubstantially outside the cross section of the cylindrical boundary by adistance greater than about 10 percent of the diameter of thecylindrical boundary.

[0034] In this Example, the second level interconnects in a chip scalepackage according to the invention is constructed having dimensions asfollows: the ball-to-ball pitch is about 0.75 mm; the second levelcontact pad diameter is about 0.35 mm; and the diameter of the nominallycylindrical region of the fill volume overlying the second levelinterconnect site is about 0.4 mm.

EXAMPLE 2

[0035] Selected first and second fill materials.

[0036] This example illustrates construction of chip scale packageshaving various combinations of fill materials and the first and secondfill zones. Particularly, in a first configuration, according to theinvention, a second fill material having a specific elastic modulusabout 7.5 GPa was employed together with a first fill material having aspecific elastic modulus about 0.4 GPa; in a second configuration, alsoaccording to the invention, a second fill material having a specificelastic modulus about 7.5 GPa was employed and the second fill zone wasleft void (having a specific elastic modulus of 0); and in a thirdconfiguration, substantially the entire fill volume was filled with afill material having a specific elastic modulus about 7.5 GPa, as in aconventional package.

EXAMPLE 3

[0037] Thermal cycling of chip scale packages configured as in example2.

[0038] Chip scale package is constructed as an example 2 were subjectedto a standardized test of thermal stress. Particularly, the devices weretested for electrical continuity while being subjected to a repeatedtemperature cycle consisting of a ramp up from 0° C. to 100° C. over a10 minute period, followed by a dwell for a 10 minute period at 100° C.,followed by a ramp down from 100° C. to 0° C. over a 10 minute period,followed by a dwell for a 10 minute period at 0° C.

[0039] Generally, the packages according to the invention survivedlonger in this test than the conventional package (about 30% longer),and packages according to the invention having substantially no fillmaterial in the first fill zone survived longer in this test (about 20%longer) than the packages having a low specific elastic modulus adhesivein the first fill zone.

[0040] Other embodiments are within the following claims.

What is claimed is:
 1. A flip chip package, comprising an integratedcircuit chip having interconnect bumps formed on input/output pads in aspecified arrangement, and a package substrate having a plurality ofbond pads in a complementary arrangement, wherein interconnectionbetween the bumps on the integrated circuit chip and the respective bondpads on the package substrate is established by direct mating of thebump surfaces with the respective bond pads and thermo-mechanicaldeformation of the bumps.
 2. The flip chip package of claim 1 whereinthe bump is constructed of a material selected to provide low yieldstrength, high ductility, and an oxidation- and corrosion-resistant bumpsurface.
 3. The flip chip package of claim 2 wherein the bumps areformed of gold or a gold alloy.
 4. The flip chip package of claim 1wherein the bumps are formed on the input/output pads of the integratedcircuit chip by a stud bumping process.
 5. The flip chip package ofclaim 1 wherein the bumps are formed on the input/output pads of theintegrated circuit chip by a solder bumping process.
 6. The flip chippackage of claim 1 wherein the bumps are formed on the input/output padsof the integrated circuit chip by an electroplating process.
 7. A methodfor forming a flip chip package, comprising providing an integratedcircuit chip having interconnect bumps formed on input/output pads in aspecified arrangement, each said interconnect bump having low yieldstrength, high ductility, and an oxidation- and corrosion-resistantsurface; providing a package substrate having a plurality of bond padsin an arrangement complementary to the specified arrangement ofinput/output pads on the integrated circuit chip; contacting the bumpswith the respective bond pads on the package substrate; andthermo-mechanically treating the bumps to form solid-state connectionsof the bumps with their respective bond pads.
 8. The method of claim 7wherein the thermo-mechanically treating step comprises concurrentlyforcing the bump against the pad and heating the bump and pad.
 9. A flipchip package, comprising an integrated circuit chip having interconnectbumps formed on input/output pads in a specified arrangement in asurface thereof, and a package substrate having a plurality of bond padsin a complementary arrangement in a subjacent surface of the packagesubstrate, wherein second level interconnect sites are arranged in asecond surface of the package substrate, and second level interconnectstructures are connected to the respective second level interconnectsites, and wherein a fill volume is defined between the integratedcircuit chip and the package substrate, the fill volume being at leastpartly filled with at least one fill material, each said fill materialhaving a selected specific elastic modulus, wherein regions of the fillvolume that overlie the second level interconnect sites contain a lowerspecific elastic modulus fill material.
 10. The flip chip package ofclaim 9 wherein the fill volume includes a first fill zone comprising aplurality of generally columnar volumes, generally overlying theplurality of second level interconnect sites; and the second fill zoneconsists of the remainder of the fill volume.
 11. The flip chip packageof claim 10 wherein at least a part of the first fill zone contains afirst material having a lower specific elastic modulus, and at least apart of the second fill zone contains a second material having a higherspecific elastic modulus.
 12. The flip chip package of claim 11 whereinthe first fill material has a specific elastic modulus less than about0.5 GPa.
 13. The flip chip package of claim 11 wherein the second fillmaterial has a specific elastic modulus greater than about 5 GPa. 14.The flip chip package of claim 13 wherein the second fill material has aspecific elastic modulus in a range about 5 GPa to about 15 GPa.
 15. Theflip chip package of claim 11 wherein the second fill material comprisesan epoxy.
 16. The flip chip package of claim 15 wherein the second fillmaterial comprises an anhydride curable epoxy.
 17. The flip chip packageof claim 11 wherein the first fill zone comprises voids in the fillmaterial within the fill volume.
 18. The flip chip package of claim 11wherein the first fill material comprises an adhesive.
 19. The flip chippackage of claim 18 wherein the first fill material comprises a siliconadhesive.
 20. A method for making a flip chip package configured forinterconnection to a printed circuit board, comprising providing anintegrated circuit chip having a surface; providing a package substratehaving a first surface and a second surface, the second surface beingprovided with a plurality of second level interconnect sites, thelocations of the second level interconnect sites defining a plurality offirst fill zone areas over the first surface of the package substrate,the remainder of the first surface of the package substrate constitutinga second fill zone area; dispensing at least a second fill material,having a specific elastic modulus greater than about 5 GPa, within thesecond fill zone area on the first surface of the package substrate; andassembling the integrated circuit chip and the package substrate so thatthe second fill material is confined in a second fill zone within avolume defined between the integrated circuit chip surface and the firstsurface of the package substrate.
 21. The method of claim 20 wherein thesecond fill material has a specific elastic modulus in a range about 5GPa to about 15 GPa.
 22. The method of claim 20, further comprising,prior to assembling the package, dispensing a first fill material havinga specific elastic modulus less than about 0.5 GPa within the first fillzone area on the first surface of the package substrate.